Error detector for modified duobinary signals

ABSTRACT

A modified duobinary signal is separated into two (odd and even) pulse trains, each of which is representative of a bipolar pulse train. Each representative bipolar pulse train has a bit rate one-half that of the modified duobinary signal. Violations of the modified duobinary coding rules appear as violation of the bipolar coding rules. The bipolar violations which occur are detected separately for the odd and even pulse trains. The detected errors are read into an error combiner and are read out serially at the original modified duobinary bit rate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to error detection in digital transmissionwherein correlative level coding is employed, and more particularlyrelates to error detection for a modified duobinary signal.

2. Background of the Invention

Duobinary systems are explained, for example, in an article appearing inIEEE Transactions on Communications and Electronics, vol. 82, May 1963,pp. 214-218, as well as a variety of generally available publicationssuch as IEEE Spectrum article February 1966. In particular, theduobinary system is disclosed and claimed in U.S. Pat. No. 3,238,299entitled, "High-Speed Data Transmission System" by the present inventor.Subsequent publications by this inventor have disclosed a number ofvariations in the basic duobinary concepts. The duobinary technique, asoriginally developed, contemplated a baseband three-level, correlativelevel-coded signal in which the frequency spectrum of the wave increasedwith decreasing frequency, reaching a maximum value at a frequency whichwas essentially zero. Important among the additional publications ofinterest is the article entitled, "Correlative Digital CommunicationTechniques," appearing in IEEE Transactions on CommunicationsTechnology, vol. 13, June 1965, pp. 203-208. In addition, a number ofcorrelative level-coded techniques are described in U.S. Pat. No.3,388,330 entitled, "Partial Response Multilevel Data System." Moreparticularly, a technique for converting a binary signal into a modifiedduobinary signal and the particularities of the characteristics of themodified duobinary signal are described in considerable detail in U.S.Pat. No. 3,457,510 entitled, "Modified Duobinary Data Transmission" bythe present inventor. The subject U.S. Pat. No. 3,457,510 isincorporated herein by reference. A digital technique for generating amodified duobinary signal is contained in the copending application,Ser. No. 623,292, filed Oct. 17, 1975, and the present inventor is acoinventor of that application.

A technique for the detection of errors in a modified duobinary signalis disclosed in U.S. Pat. No. 3,461,426. In the subject error detectionpatent, it is to be noted that the transmitted modified duobinarywaveform and the binary waveform reconstituted therefrom by decoding aremonitored and coincidences detected between extreme level signals of theformer and correlated portions of the latter to indicate errors. Incontrast, the error detector of the present invention does not requirethe use of the binary output signal obtained by decoding in thereceiving circuitry. Further, the prior error detection technique doesnot teach the concept of dividing the modified duobinary into two (oddand even) pulse trains each of which is representative of a bipolarpulse train.

SUMMARY OF THE INVENTION

The error detector of the subject invention contemplates dividing themodified duobinary signal, having a predetermined bit rate, into firstand second pulse trains, each of which is representative of a bipolarpulse train, and each having a bit rate equal to one-half saidpredetermined bit rate. The pulse trains are delayed one from the otherby one bit interval. Errors which occur in each of the separate pulsetrains are separately detected and serially combined to obtain the erroroutput signal for the modified duobinary pulse train.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a waveform diagram showing transmitted and received modifiedduobinary pulse trains and the odd and even bipolar pulse trains thatmay be derived from the received modified duobinary pulse train.

FIG. 2 is a block diagram of the error detector of the invention.

FIG. 3 is a more detailed block diagram of the pulse train divider.

FIG. 4 is a more detailed block diagram of the clock divider.

FIG. 5 is a block diagram illustrating the two bipolar error detectorsand the input paths including delay circuits 10 and 12.

FIG. 6 is a block diagram of the error combiner; and

FIG. 7 is a waveform diagram showing the detection of an error in theeven bipolar error detector.

Table I illustrates the positive and negative representations of thetime slots for the waveform polarity and further illustrates the odd andeven representations that will be obtained from the waveformT-characteristic.

DETAILED DESCRIPTION OF THE INVENTION

In general, the modified duobinary waveform operated upon by the presentinvention comprises a three-level signal in which the extreme levelsrepresent one binary state, such as MARK, and the center or intermediatelevel signal represents the other binary state, such as SPACE. Thisconvention can, of course, be reversed. This signal follows apredetermined set of rules. These rules may be readily understood bygrouping all of the successive MARKS in pairs and assigning the pairnumber of each MARK as illustrated in FIG. 1 for waveform T. SuccessiveMARKS are indicated by the numerals 1 and 2, with a repetition of thisnumbering for the next pair of MARKS. A MARK bearing number 1 in a pairof two successive MARKS will be seen to always have the oppositepolarity relative to the previous MARK which, of course, carries thenumber 2. The polarity of the MARK, identified by number 2, relative tothe previous MARK bearing number 1, is governed by a set of odd and evenrules, as in the straight duobinary system and method. Specifically, ifthe number of intervening SPACES between a pair of MARKS numbered 1 and2 is odd, then the polarities of these two MARKS are opposite; and ifthe number of intervening SPACES between a pair of MARKS numbered 1 and2 is even, then the polarities of these two marks are the same.

By referring to waveform R, FIG. 1, it is seen that an error has beenintroduced at time slot 6. It is apparent that at this point an errordetector would not recognize the negative pulse in time slot 6 as anerror, since the number of intervening SPACES from the last MARK iseven, and since the previous MARK was negative, the appearance of anegative in time slot 6 would not be indicative of an error. Followingthe rules as set forth hereinabove, it is apparent that the presence ofa negative MARK in time slot 8 is indicative of the fact that an errorhas occurred either by the presence of this MARK in time slot 8 or bythe presence of the previous MARK in time slot 6. Thus, an error may bedetected by the violation of the modified duobinary coding rules.

Waveforms A and B in FIG. 1 show, respectively, the odd and even bipolarwaveforms which may be derived from the modified duobinary pulse train.The waveforms as shown may be considered to be return-to-zero or 50%duty cycle bipolar signals at the bit rate equal to half of the modifiedduobinary waveform. The coding rule for the bipolar signal is thatsuccessive MARKS will have opposite polarities. Referring now to thewaveform B, wherein the error occurs because time slot 6 is associatedwith this waveform, it is to be noted that here again the violation ofthe modified duobinary coding rules also appears as a violation of thebipolar coding rules. Thus, detection of the bipolar violations of theodd and/or even wave forms will result in the detection of the errorswhich have occurred during transmission of the modified duobinary pulsetrain. Thus, the essence of this error detection technique is to regardthe modified duobinary signal as an algebraic sum of two independentbipolar pulse trains, delayed with respect to each other by T seconds,where T is the bit interval duration of the modified duobinary, and 1/Tis the bit rate in bits per second of the modified duobinary pulsetrain. This representation is valid as shown in a waveform diagram ofFIG. 1, as it conforms with the rules and patterns of the modifiedduobinary signal. The pulse train R is modified duobinary, followinglegitimate duobinary rules. Waveform A represents the odd pulses only(1, 3, 5, etc.) and waveform B represents only the even pulses (2, 4, 6,etc.). An algebraic sum of waveforms A and B is, indeed, R. Except forthe error which occurs at time slot 6, waveforms A and B follow thebipolar pulse train rules in that successive MARKS alternate inpolarity. Thus, the keypoint in the implementation is to separate thepulse train R in FIG. 1 into bipolar pulse trains. A and B and to checkthese bipolar waveforms separately for bipolar violations. In order toeffectuate this representation using a binary logic, it is necessary toapproach the required result in a somewhat different manner.

Referring now to FIG. 2, which shows a general block diagram of thepreferred embodiment of the invention, the received modified duobinarysignal as shown at R, FIG. 1, is applied to pulse train divider 4 viapath 2. Pulse train divider 4 separates the waveform R into waveforms Cand D, as shown in FIG. 7. By referring to FIG. 7, it may be seen thatwaveform C is a unipolar representation of the positive pulses ofwaveform R and that waveform D is a unipolar representation of thenegative pulses of waveform R. With respect to the latter, the pulsesare shown as positive in waveform D. Thus, as will become apparentlater, the bipolar signals are representative only because they arederived from a unipolar representation. A clock signal at the pulserepetition rate of the modified duobinary signal in FIG. 2 is appliedfrom clock 34 via path 36 to pulse train divider 4. The clock 34 may bea local clock, but most often is derived from the incoming data, as iswell known in the art. Techniques for deriving a local clock are wellknown and these will not be described in this specification. It is alsoseen that the output from clock 34 is applied to clock divider 40, andclock divider 40 divides the clock rate in half and, in addition,provides 42 and 44 at one-half of the clock 34 rate, but in oppositephases one from the other. Reverting now to the output of pulse traindivider 4, it is to be seen that two similar circuit paths are employed.The first path includes delay 10 and bipolar error detector 22, and thesecond includes delay 12 and bipolar error detector 24. Since theseoperate similarly, only the upper one will be considered in thefollowing discussion. Outputs 6 and 8, i.e., waveforms C and D, areapplied to inputs of delay 10 along with the input 42 from clock divider40. Delay 10 provides, on output path 14, a delayed representation ofthe input signal on path 6 and, at output path 16, the delayed outputrepresentation on path 8. It should be noted that because of the timingfrom clock divider 40, the representations on paths 14 and 16 areapplicable only to the odd time slots of the original waveform. Inaddition to the representations on paths 14 and 16, the originalwaveforms on paths 6 and 8 are applied to bipolar error detector 22 aswell as the timing signal along path 42 from clock divider 40. Thebipolar error detector detects pipolar error violations which may occurby comparing the polarities of previous and present MARKS, and appliesthese via path 26 to error combiner 30, which combines the errors fromboth paths and applies these to output 32. Pertinent portions of theerror detector shown in FIG. 2 will be explained in more detailhereinbelow.

A technique for generating waveforms C and D is shown in FIG. 7 isillustrated in FIG. 3. The modified duobinary waveform, which isreceived from the transmission facility, is applied to center-taptransformer 46 via path 2 and provides the positive and negativeoutputs, respectively, at paths 48 and 50. The positive output isapplied to top slicer 52, which identifies the pressence of a positivepulse, such as is shown in time slots 1 and 2 of FIG. 7. The bottomslicer 54 identifies the negative- going pulses such as is shown in timeslots 3 and 8 of waveform R, FIG. 7. These pulses are amplified inamplifiers 56 and 58, which are then applied, respectively, toflip-flops 60 and 62 from which the output waveforms C and D areobtained from the Q-outputs of the respective flip-flops. The timinginformation for flip-flops 60 and 62 is applied via path 36 from clock34 to the clock inputs of the respective flip flops. It should be notedthat in certain applications, the waveforms C and D, i.e., the positiverepresentation in a unipolar format of the positive and negative pulsesof a modified duobinary waveform, may already be available fromequipment associated with the error detector, and thus the elements asshown in FIG. 3 would not be required.

In order to obtain the odd and even output as disclosed in theconceptual discussion above and illustrated in FIG. 1, it is necessaryto derive the clock pulse signals, each having a clock rate of one-halfthe bit of the modified duobinary signal and each being of oppositephase one from the other. This is accomplished by clock divider 40,which is shown in FIG. 4. The clock frequency in the form of a squarewave appears on path 38 and is applied to inverter 64. Inverter 64 mayinclude a plurality of inverters as is necessary to obtain the timedelay required to maintain timing integrity. The output of inverter 64is applied to a D-type flip-flop 66 which has the Q output and the Dinput strapped as shown. When the positive-going edge of the square waveappears at the clock pulse input, the Q-output becomes Q, i.e., the sameas the D-input. Equivalently, Q always changes state. Further, it isapparent that Q and Q have opposite phases. Thus, the outputs Q and Qare square waves at a frequency which is half that of the modifiedduobinary bit rate, and they have opposite phases. Essentially this isthe same as having the clock square waves delayed by T seconds, where Tis equal to the reciprocal of the modified duobinary bit rate.NAND-gates 70 and 72 operate as inverters to clean up the waveforms.These are followed by an RC differentiator for shaping and furtherclean-up by the NAND-gates 90 and 92, which provide the required dividedclock pulses which have opposite phases. One phase of the clock output,i.e., that which is provided on path 44, is shown in FIG. 7 as waveform44.

The delay and bipolar error detector circuit arrangements illustrated inblock form in FIG. 2 are shown in more detail in FIG. 5. As notedhereinabove, the circuits for the odd and even time slots are identical,and therefore only the operation of one will be described in detailsince the operation of the other is identical, except for the time slotsfor which they are applied. In this case, the discussion will focus onthe even time slots, i.e., the lower circuit configuration, since thewaveform R, as shown in FIG. 1, has an error in the even time slot no.6. The only essential difference between the two is in the phase of theclock pulses, as described hereinabove. Each of these circuits detectserrors. One detects the errors caused by bipolar violations of the oddbits, and the other detects errors cause by bipolar violation of theeven bits. Thus, the two clocks, in effect, separate odd from even bitsthat appear at waveforms C and D along input paths 6 and 8. In themodified duobinary waveform, if one considers either the even only orodd only bits, then the successive pulses must alternate in polarity.Any departure from this rule constitutes a violation which indicates anerror. In FIG. 5, the delay 10 is shown as J-K flip-flop having a timinginput to select only the odd bits, while the delay 12 is shown as a J-Kflip-flop with timing, such as to select only the even bits. In thefollowing discussion, only the operation of the detection circuitry fordetecting bipolar violations of the even bits will be considered.

The function of delay 12 is to "remember" the previous +1 represented inwaveform C, applied on path 6, or to "remember" the previous -1represented in waveform D, which is applied on path 8. This may bereadily accomplished by using a J-K flip-flop as shown in FIG. 5. Forexample, a +1 represented by waveform 6 will result in the Q-output offlip-flop 12 being positive or high; however, should the input on path8, i.e., waveform D, be positive, representing -1, Q will be high and Qwill be low. This "reading in" into flip-flop 12 occurs at the instantof clock pulse on the input CP. Table 1 illustrates the positive andnegative representations of the time slots for the waveform polarity,both prior to and subsequent to the representations of the waveforms Cand D, and further illustrates the odd and even representations thatwill be obtained from the waveform T-characteristic, as illustrated inFIG. 1. Thus, no error occurrences appear in Table 1 as illustrated. Itis interesting to note that the odd and even waveforms show a "bipolar"representation in that positive representations alternately occur in theC- and D- outputs for the odd time slots and also for the even timeslots, as indicated. Reverting back to the waveform diagrams, FIG. 7,the representations at the Q and Q-outputs of delay 12 are shown at 18and 20. When these, in conjunction with the inputs on paths 6 and 8, arecombined in the logic gating arrangement consisting of NAND-gates 102,104 and 106, it is noted that the output of NAND-gate 102 is alwayspositive, i.e., a+1, during the intervals in question, whereas theoutput of NAND-gate 104 is positive, i.e., a+1, except for one timeslot, thus, indicating that an error had occurred. Note that since thisis detection only, the actual time of occurrence of the error is notobtained. The 1 and 0 inputs to NAND-gate 106 then cause an output pulseto appear as illustrated in waveform 106, which is then timed throughflip-flop 108 to appear on output path 28. Stated in a more precisemanner, when waveform C has a positive pulse and Q is positive, thisindicates an error, because two positive successive pulses appear, whichviolates the bipolar pattern. Similarly for simultaneous occurrences ofpositive pulses in waveform C and a positive output at Q. The threeNAND-gates which follow each of the respective J-K flip-flops constitutean AND-OR combination. This is well known and may be illustrated usingthe following Boolean equation:

    W = (CQ) DQ = CQ + DQ.

thus, the output W of NAND-gate 106 is CQ + DQ. This means thatsimultaneous occurrence of either C and Q or D and Q will cause anoutput pulse indicating an error.

Next, the odd and even errors must be combined. This is shown by theerror combiner block diagram in FIG. 6. Once again, the three NAND-gatesconstitute an AND-OR combination. The three NAND-gates are 110, 112, and114, and their function is to combine odd and even output errors. Thus,the output on path 16 provides all errors, both odd and even. Gate 116is merely an inverter to "clean" the error output waveform. The outputfrom NAND-gate 114 occurs when one of the two possible events occurs;simultaneous occurrence of a positive output on path 26 and appearanceof the clock pulse on path 42. This indicates an odd error. The secondpossible event is simultaneous occurrence of a positive output on path28 in conjunction with a clock pulse on path 44. This indicates an evenerror.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

What is claimed is:
 1. An error detector for detecting errors in amodified duobinary pulse train, which comprises:means for converting themodified duobinary pulse train into a first unipolar pulse trainrepresenting the positive pulses at a first output, and a secondunipolar pulse train representing the negative pulses at a secondoutput; delay means for providing a first delayed representation of thefirst and second unipolar pulse trains for only the odd bit times, and asecond delayed representation of the first and second unipolar pulsetrains for only the even bit times; and logic means operativelyconnected to said delay means and to said converting means for detectingcoincidences of occurrence of successive pulses in the first or secondpulse trains only for the even or odd bit times.
 2. An error detector inaccordance with claim 1 wherein said logic means further comprises:afirst gating means having a plurality of inputs operatively connected toreceive the first unipolar pulse train and the delayed representations,said first gating means providing an output error signal whenever abipolar violation occurs in said first bipolar pulse train; a firstflip-flop connected to receive the output error signal from said firstgating means, said first flip-flop responsive to error input signals toprovide delayed output error signals; a second gating means having aplurality of inputs operatively connected to receive the second unipolarpulse train and the delayed representations, said second gating meansproviding an output error signal whenever a bipolar violation occurs insaid second bipolar pulse train; a second flip-flop connected to receivethe output error signal from said second gating means, said secondflip-flop responsive to error input signals to provide delayed outputsignals; and means for combining the output error signals from saidfirst and second flip-flops.
 3. An error detector in accordance withclaim 2 wherein said means for combining further comprises:timing meansproviding a first timing signal at one-half the bit rate and a secondtiming signal at the same one-half bit rate but delayed so as to be outof phase with said first timing signal; a third gating means having asone input said first timing signal and having as a second input theoutput of said first flip-flop, and having an output; a fourth gatingmeans having as one input said second timing signal and having as asecond input the output of said second flip-flop, and having an output;a fifth gating means having a one input connected to the output of saidthird gating means, a second input connected to the output of saidfourth gating means, and having an output; an inverter having an inputconnected to the output of the fifth gating means and having an output.4. An error detector for detecting errors in a modified duobinary pulsetrain, which comprises:timing means; pulse train dividing means having afirst input connected to said timing means, a second input connected toreceive said modified duobinary pulse train, said dividing meansproviding a unipolar pulse train at a first output which isrepresentative of the positive pulses, and a second output which isrepresentative of said negative pulses of the modified duobinary pulsetrain; a first delay means for combining the first and second divideroutputs to obtain a binary representation of the odd bits of themodified duobinary signal, and the complements thereof, having one inputconnected to said pulse divider first output, a second input connectedto said timing means, having a third input connected to said pulsedivider second output, and having first and second outputs; a seconddelay means for combining the first and second pulse divider outputs toobtain a binary representation of the even bits, and the complementsthereof, having one input connected to said pulse divider first output,a second input connected to said timing means, and a third inputconnected to said pulse divider second output, and having the first andsecond outputs; a first error detection means having four inputs and anoutput, the first being connected to said pulse divider first output,the second input being connected to said pulse divider second output,the third input connected to the first output of said first delay means,and a fourth input connected to the second output of said first delaymeans; a second error detection means having three inputs and an output,the first input being connected to said pulse divider first output, thesecond input being connected to said pulse divider second output, thethird input being connected to the first output of said second delaymeans, and a fourth input being connected to the second output of saidsecond delay means; and error combining means having one input connectedto the output of said first error detection means, a second inputconnected to the output of said second error detection means, and a pairof inputs connected to said timing means, and having an output. 5.Apparatus for detecting errors in a modified duobinary signal having topand bottom extreme levels, which comprises:clock means having an outputand having a clock pulse rate equal to the bit rate of said modifiedduobinary signal; pulse train dividing means for forming first andsecond binary pulse trains from said modified duobinary signal, having afirst input connected to the output of said clock signal and having asecond input connected to receive said modified duobinary signal,providing at a first output said first binary pulse train whichcomprises all of the top extreme levels of said modified duobinarysignal as one binary state and the absence of top extreme levels as theother state, and providing at a second output said second binary pulsetrain which comprises all of the bottom extreme levels of said modifiedduobinary signal as said one binary state and the absence of bottomextreme levels as the other said state; a clock divider having as oneinput the output clock pulses from said clock means, having at a firstoutput a half-rate clock signal of a first phase and having at a secondoutput a half-rate clock signal of a second phase which is 180° fromsaid first phase; a first delay means for combining the first and secondbinary pulse trains to obtain a binary representation of the odd bits,and the complement thereof, of the modified duobinary signal, said firstdelay means having a first input connected to receive said first binarypulse train, having a second input connected to receive said secondbinary pulse train, having a third input connected to the first outputof said clock divider and having first and second outputs; a seconddelay means for combining the first and second binary pulse trains toobtain a binary representation of the even bits, and the complementthereof, of the modified duobinary signal, said second delay meanshaving a first input connected to receive said first binary pulse train,having a second input connected to receive said second binary pulsetrain, having a third input connected to the second output of said clockdivider, and having first and second outputs; a first error detectionmeans for detecting errors occurring in the binary representation of theodd bits of the modified duobinary signal, said first error detectionmeans having first and second inputs, respectively, connected to thefirst and second outputs of said first delay means, having third andfourth inputs, respectively, connected to the first and second outputsof said pulse train dividing means and having an output; a second errordetection means for detecting errors occurring in the binaryrepresentation of the even bits of the modified duobinary signal, saidsecond error detection means having first and second inputs,respectively, connected to the first and second outputs of said seconddelay means, having third and fourth inputs, respectively, connected tothe first and second outputs of said pulse train dividing means, andhaving an output; and error combining means for combining the errorinformation from said first and second error detection means, said errorcombining means having a first input connected to the output of saidfirst error detection means, having a second input connected to theoutput of said second error detection means, having third and fourthinputs, respectively, connected to the first and second outputs of saidclock dividing means and having an output.
 6. Apparatus in accordancewith claim 5 wherein said pulse train dividing means comprises:couplingmeans having an input connected to receive said modified duobinarysignal, providing at a first output the top extreme levels as positivepulses and at a second output the bottom extreme levels as positivepulses; first slicing means having an input connected to the firstoutput of said coupling means and providing an output; first pulsereshaping means having a first input connected to the output of saidfirst slicing means, and having a second input connected to the outputof said clock means and providing at an output said first binary pulsetrain; second slicing means having an input connected to the secondoutput of said coupling means and having an output; and second pulsereshaping means having a first input connected to the output of saidsecond slicing means, having a second input connected to the output ofsaid coupling means and providing at an output said second binary pulsetrain.
 7. Apparatus in accordance with claim 6 wherein said first errordetection means further comprises:a first AND-OR logic means having afirst input connected to the output of said first pulse reshaping means,having a second input connected to the output of said second pulsereshaping means, having a third input connected to the first output ofsaid first delay means and having a fourth input connected to the secondoutput of said first delay means and having an output; and pulseretiming means having one input connected to the output of said AND-ORlogic means and having a second input connected to the first output ofsaid clock divider and having an output.
 8. Apparatus in accordance withclaim 7 wherein said second error detection means further comprises:asecond AND-OR logic means having a first input connected to the firstoutput of said pulse reshaping means, having a second input connected tothe output of said second pulse reshaping means, having a third inputconnected to the first output of said second delay means, having afourth input connected to the second output of said second delay meansand providing an output; and pulse retiming means having a first inputconnected to the output of said AND-OR logic means, having a secondinput connected to the second output of said clock divider and having anoutput.